Minsoo Rhu

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Tor M. Aamodt18
Scott E. Reed16
Dragomir Anguelov16
Christian Szegedy16
Yangqing Jia16
12Mike O'Connor
12Stephen W. Keckler
11Shenggang Chen
11Xiaowen Chen
11Shuming Chen

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Priority-based cache allocation in throughput processors
GPUs employ massive multithreading and fast context switching to provide high throughput and hide memory latency. Multithreading can Increase contention for various system resources, however, that may result In suboptimal utilization of shared resources. Previous research has proposed variants of throttling thread-level parallelism to reduce cache… (More)
The dual-path execution model for efficient GPU control flow
Current graphics processing units (GPUs) utilize the single instruction multiple thread (SIMT) execution model. With SIMT, a group of logical threads executes such that all threads in the group execute a single common instruction on a particular cycle. To enable control flow to diverge within the group of threads, GPUs partially serialize execution and… (More)
Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation
Current GPUs maintain high programmability by abstracting the SIMD nature of the hardware as independent concurrent threads of control with hardware responsible for generating predicate masks to utilize the SIMD hardware for different flows of control. This dynamic masking leads to poor utilization of SIMD resources when the control of different threads in… (More)
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design
—The most widely used machine learning frameworks require users to carefully tune their memory usage so that the deep neural network (DNN) fits into the DRAM capacity of a GPU. This restriction hampers a researcher's flexibility to study different machine learning algorithms, forcing them to either use a less desirable network architecture or parallelize… (More)
A locality-aware memory hierarchy for energy-efficient GPU architectures
As GPU's compute capabilities grow, their memory hierarchy increasingly becomes a bottleneck. Current GPU memory hierarchies use coarse-grained memory accesses to exploit spatial locality, maximize peak bandwidth, simplify control, and reduce cache meta-data storage. These coarse-grained memory accesses, however, are a poor match for emerging GPU… (More)
CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well on their SIMD pipelines. To do this, each SIMD lane is considered to execute a logical thread where hardware ensures that control flow is accurate by automatically applying masked… (More)
Virtualizing Deep Neural Networks for Memory-Efficient Neural Network Design
The most widely used machine learning frameworks require users to carefully tune their memory usage so that the deep neural network (DNN) fits into the DRAM capacity of a GPU. This restriction hampers a researcher's flexibility to study different machine learning algorithms, forcing them to either use a less desirable network architecture or parallelize the… (More)
GPUVolt: modeling and characterizing voltage noise in GPU architectures
Voltage noise is a major obstacle in improving processor energy efficiency because it necessitates large operating voltage guardbands that increase overall power consumption and limit peak performance. Identifying the leading root causes of voltage noise is essential to minimize the unnecessary guardband and maximize the overall energy efficiency. We… (More)