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A 14nm logic technology using 2 nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal(More)
A mixed potential integral equation (MPIE) technique combined with fast multi-layer Green's functions and Gaussian Jacobi high order techniques is used to compute the 3-D frequency dependent inductances and resistances in lossy multi-layered substrate. Compared to FastHenry, a multipole-accelerated 3-D inductance extraction program, the algorithm presented(More)
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