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Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In(More)
—An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS(More)
—A four-terminal RF MOSFET model to accurately describe the three-port network characteristics is presented. It has been found that the short-channel effect in the source-to-drain capacitance plays a critical role in predicting behavior of the MOSFET in the common-gate/body configuration. Performance of the developed model was verified with the device(More)
In this paper, an integrated electrocardiogram (ECG) signal-processing scheme is proposed. Using a systematic wavelet transform algorithm, this signal-processing scheme can realize multiple functions in real time, including baseline-drift removal, noise suppression, QRS detection, heart beat rate prediction and classification, and clean ECG reconstruction.(More)
An integrated CMOS ultrawideband wireless telemetry transceiver for wearable and implantable medical sensor applications is reported in this letter. This high duty cycled, noncoherent transceiver supports scalable data rate up to 10 Mb/s with energy efficiency of 0.35 nJ/bit and 6.2 nJ/bit for transmitter and receiver, respectively. A prototype wireless(More)
— In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression.(More)
A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and(More)