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In this paper we present a test structure and design methodology for testing, characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the signal degradation through TSVs due to resistive shorts and variations in TSV. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery(More)
We propose a dynamically reconfigurable SRAM architecture for low-power mobile multimedia applications. Parametric failures due to manufacturing variations limit the opportunities for power saving in SRAM. We show that, using a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits, ~45% savings in memory(More)
ŠDIE-TO-DIE AND WITHIN-DIE statistical variations in process parameters result in parametric failures (read, write, access, and hold failures) in SRAM cells, thereby degrading design yield. The principal reason for parametric failures is intradie variation in the cell transistors' threshold voltage due to random dopant fluctuations (RDFs). 1 On the other(More)
This work proposes a low power methodology for video framebuffers to preserve the perceptual quality while reducing SRAM power. The bank-wise voltage scaling combined with error masking circuitry is proposed where voltage domains are separated according to the importance of luminous and color channels. The implementation may apply to standard embedded(More)