Mingshuo Wang

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A 1.0GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42 fJ/Conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block(More)
In this paper, a high-precision and high-linearity calibration is introduced for dynamic comparator offset using I-MOS capacitors. After calibration, the offset can be reduced from 29.9 mV to 66 μV (one sigma) at 2GHz working clock. Simulation results show that the SFDR and the SNDR can be improved 20dB in a case of 12bit 50MS/s successive(More)
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