—A new technique to de-embed the contributions of parasitic structures from transmission line measurements is presented and applied to microstrip lines fabricated in 90-and 130-nm RF-CMOS technologies. De-embedded measurements are used to extract characteristic impedance, attenuation constant, group delay, and effective permittivity. The effective thickness… (More)
Because of the popularity of portable devices and wireless LANs based on IEEE 802.11 standard, the mobility in wireless network environment become more important. There are two important issues to be addressed in order to support real-time service across wireless networks. One is high transmission data rate; the other is low handoff delay latency. In this… (More)
Power processes for high-speed digital design.
This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a <i>V</i> <sub>GS</sub> lower than zero <i>K</i> 3<i>g</i> <i>m</i> point. This <i>V</i> <sub>GS</sub> difference is attributed to the nonlinear output conductance and the cross terms using a… (More)
Ordinary differential equations usefully describe the behavior of a wide range of dynamic physical systems. The particle swarm optimization PSO method has been considered an effective tool for solving the engineering optimization problems for ordinary differential equations. This paper proposes a modified hybrid Nelder-Mead simplex search and particle swarm… (More)
The purpose of this paper is to solve the problem of protecting aerial lines from high impedance faults (HIFs) in distribution systems. This investigation successfully applies 3I 0 zero sequence current to solve HIF problems. The feature extraction system based on discrete wavelet transform (DWT) and the feature identification technique found on statistical… (More)
The low-loss single semi-coaxial (S-SC) and differential semi-coaxial (D-SC) interconnects based on a standard 0.18-gm CMOS process are presented for the first time. Compared to the attenuation constant (a) reported for microstrip and CPW interconnects in CMOS process, the S-SC line shows the lowest loss of 0.90 dB/mm at 50 GHz. The D-SC line also presents… (More)
This work examines the intermodulation linearity of 90 nm RF CMOS using IP3 measurement, BSIM4 based simulation, and first order theory. V<sub>GS</sub>, V<sub>DS</sub>, and device width dependences are examined. Guidelines to accurately identifying the sweet spot biasing current for larger devices used in RFIC design are provided.