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—A new technique to de-embed the contributions of parasitic structures from transmission line measurements is presented and applied to microstrip lines fabricated in 90-and 130-nm RF-CMOS technologies. De-embedded measurements are used to extract characteristic impedance, attenuation constant, group delay, and effective permittivity. The effective thickness… (More)
Power processes for high-speed digital design.
This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a <i>V</i> <sub>GS</sub> lower than zero <i>K</i> 3<i>g</i> <i>m</i> point. This <i>V</i> <sub>GS</sub> difference is attributed to the nonlinear output conductance and the cross terms using a… (More)
The low-loss single semi-coaxial (S-SC) and differential semi-coaxial (D-SC) interconnects based on a standard 0.18-gm CMOS process are presented for the first time. Compared to the attenuation constant (a) reported for microstrip and CPW interconnects in CMOS process, the S-SC line shows the lowest loss of 0.90 dB/mm at 50 GHz. The D-SC line also presents… (More)
This work examines the intermodulation linearity of 90 nm RF CMOS using IP3 measurement, BSIM4 based simulation, and first order theory. V<sub>GS</sub>, V<sub>DS</sub>, and device width dependences are examined. Guidelines to accurately identifying the sweet spot biasing current for larger devices used in RFIC design are provided.
Design, characterization, and modeling of differential semicoaxial interconnects based on a standard 0.18-mum CMOS process are presented for the first time. The differential semicoaxial line shows a low differential-mode attenuation constant of ~1.00 dB/mm at 50 GHz and a slow-wave factor above 3.1 over a wide frequency range. The characteristics of… (More)