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Charge pump with perfect current matching characteristics in phase-locked loops
Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLLExpand
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A Study of BER-Optimal ADC-Based Receiver for Serial Links
TLDR
Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. Expand
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An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM
TLDR
In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). Expand
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An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks
TLDR
In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory, where computation is deeply embedded into the memory (SRAM). Expand
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A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7- $\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation
TLDR
A video graphics array (VGA) (640 <inline-formula> <tex-math notation="LaTeX">$\times $ ) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap pixel structure, and consumes only 160 mW for VGA output at 60 frames/s. Expand
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A 3D Touchless Hand Navigation Sensor for Small-Size and Low-Power Applications
TLDR
A hand navigation sensor working as a 3D touchless joystick or a mouse is presented for small-size and low-power applications. Expand
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Custom test chip for system-level ESD investigations
A test-chip for monitoring soft failures is presented. Diagnostics include logic circuit upset detection, substrate potential latchup monitors, input glitch detectors, system IDDQ monitors, and USBExpand
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A 640×480 Indirect Time-of-Flight CMOS Image Sensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation Scheme
TLDR
An indirect Time-of-Flight (ToF) CMOS image sensor has been designed with 4-tap $7-\mu \mathrm{m}$ global-shutter pixel in 65-nm back-side illumination process. Expand
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Energy-efficient and high throughput sparse distributed memory architecture
TLDR
This paper presents an energy-efficient VLSI implementation of Sparse Distributed Memory (SDM) in 45 nm SOI CMOS process. Expand
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ESD protection networks for 3D integrated circuits
TLDR
The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. Expand
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