Min-Seong Choo

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In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require a timing calibration circuit for phase alignment between the PLL and(More)
In this paper, the amount of phase shift with result of the pulse injection is derived mathematically and verified by simulation. The resultant phase shift is proportional to injection pulse width, and inversely proportional to on-resistance of the switch and total capacitance parallel to injection transistor. In addition, phase shift has sinusoidal form(More)
A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter performance with low-overhead of additional circuits such as injection switches. Because the injection clock cleans the edge of the oscillator in every injection period, jitter accumulation is avoided. However, the ILO alone causes a severe reference spur owing to the(More)
A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a(More)
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