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Particle filtering is widely used in numerous nonlinear applications which require reconfigurability, fast prototyping, and online parallel signal processing. The emerging computing platform, CUDA, may be regarded as the most appealing platform for such implementation. However, there are not yet literatures exploring how to utilize CUDA for particle(More)
This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the Single-Entry-Multiple-Data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n). The SEMD can enhance the throughput by m times(More)
Constrained particle filter is widely used in indoor localization applications. With environmental information, the cascaded hypothesis modifier can improve accuracy by rejecting particles those have invalid transitions. However, the memory requirement and computation complexity of constrained particle filter are both large, and the low spatial correlations(More)
Many recent reconfigurable/multi-mode quasicyclic low density parity check (QC-LDPC) decoder designs have shown appealing implementation results in the literature. However, most of them are based on datapath multiplexing techniques with ad hoc matrix arrangement. There is still room for further interconnection reduction, throughput enhancement, and a more(More)
The sampling importance resampling particle filter (SIR PF) is a common tool for nonlinear/non-Gaussian state estimation. The SIR PF is a memory-hungry algorithm, and the estimation accuracy is better with more particles (memory). However, the SIR PF does not utilize the memory effectively. In this paper, we propose a multi-prediction (MP) PF with two-stage(More)
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