Miloslav Kubar

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− One of the recent approaches to test A/D converter performance is the so-called Servo-Loop Method. This method is aimed at the non-linearity extraction of static ADC transfer curve. In this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. The(More)
In this paper, we propose a novel versatile engine for behavioral or transistor-level design verification of data converters. This tool is dedicated to IC designers to verify static performance of the converters during their design. It is based on advanced Servo-Loop method presented in [1] and extended by features such as innovative DAC testing method(More)
While analog part of the integrated circuit covers 10% of its area its design takes 90% of the time needed to design the whole circuit. Therefore analog synthesis is very hot topic at present. It can save enormous part of the design time. This paper presents work on novel analog synthesis tool capable of choosing circuit architecture and to size its devices(More)
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