Milos Drutarovský

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This paper presents an evaluation of the Rijndael cipher, the Advanced Encryption Standard winner, from the viewpoint of its implementation in a Field Programmable Devices (FPD). Starting with an analysis of algorithm's general characteristics a general cipher structure is described. Two different methods of Rijndael algorithm mapping to FPD are analyzed(More)
The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is the General Number Field Sieve (GNFS). Recently, architectures for special purpose hardware for the GNFS have been proposed [5, 12]. One important step within the GNFS is the(More)
We demonstrate a new high-entropy digital element suitable for True Random Number Generators (TRNGs) embedded in Field Pro-grammable Gate Arrays (FPGAs). The original idea behind this principle lies in the randomness extraction on oscillatory trajectory when a bi-stable circuit is resolving a metastable event. Although such phenomenon is well known in the(More)
—General-purpose processors are not suitable for secure cryptographic key management. Secret keys are usually stored in the internal registers of the processor, and simple attacks on protocols, software/firmware or cache memory can often lead to key disclosure causing a system security failure. The paper presents a novel principle of processor extensions(More)
— Hardware implementations of cryptography face increasingly more stringent demands for lower cost and greater computational power. In order to meet those demands more efficient approaches to implementations are needed. This paper presents detailed studies of MixColumn and InvMixColumn operations used in Advanced Encryption Standard with aim at their(More)
— The paper presents a simple stochastic model of a True Random Number Generator, which extracts randomness from the tracking jitter of a phase-locked loop. The existence of such a model is a necessary condition in the security certification process. The proposed model can be used to test, in real time, the proper behavior of the generator and thus to(More)
The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, an on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry is used. In contrast with traditionally used free running oscillators, it uses and extends a recently(More)