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This paper presents a new True Random Number Generator (TRNG) based on an analog Phase-Locked Loop (PLL) implemented in a digital Altera Field Programmable Logic Device (FPLD). Starting with an analysis of the one available on chip source of randomness-the PLL synthesized low jitter clock signal, a new simple and reliable method of true randomness… (More)

We demonstrate a new high-entropy digital element suitable for True Random Number Generators (TRNGs) embedded in Field Pro-grammable Gate Arrays (FPGAs). The original idea behind this principle lies in the randomness extraction on oscillatory trajectory when a bi-stable circuit is resolving a metastable event. Although such phenomenon is well known in the… (More)

This paper presents an evaluation of the Rijndael cipher, the Advanced Encryption Standard winner, from the viewpoint of its implementation in a Field Programmable Devices (FPD). Starting with an analysis of algorithm's general characteristics a general cipher structure is described. Two different methods of Rijndael algorithm mapping to FPD are analyzed… (More)

The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is the general number field sieve (GNFS). Recently, architectures for special purpose hardware for the GNFS have been proposed. One important step within the GNFS is the factorization… (More)

- Jan Pelzl, Martin Šimka, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke +2 others
- 2005

Since the introduction of public key cryptography, the problem of factoring large composites has been of increased interest. The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factoring large integers is the general number field sieve (GNFS). One important step… (More)

The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, an on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry is used. In contrast with traditionally used free running oscillators, it uses and extends a recently… (More)

The paper presents a chaos-based True Random Number Generator (TRNG) implemented in commercially available mixed-signal PSoC reconfigurable devices without any external components. Contrary to the traditionally used sources of randomness (eg various " well-behaved " analog noise sources) it uses well-defined deterministic analog circuit that exhibits chaos.… (More)

The paper presents a simple true random number generator (TRNG) which can be embedded in digital Application Specific Integrated Circuits (ASICs) and Field Programmable Logic Devices (FPLDs). As a source of randomness, it uses on-chip noise generated in the internal analog phase-locked loop (PLL) circuitry. In contrast with traditionally used free running… (More)

— The paper presents a simple stochastic model of a True Random Number Generator, which extracts randomness from the tracking jitter of a phase-locked loop. The existence of such a model is a necessary condition in the security certification process. The proposed model can be used to test, in real time, the proper behavior of the generator and thus to… (More)

- Michal Aftanas, Jurgen Sachs, Miloš Drutarovský, Dušan Kocur
- 2009

—Precise SAR imaging of objects or detection of moving a person behind a wall with UWB radar or non-destructive testing of walls in civil engineering requires the knowledge of wall parameters like thickness and permittivity. Their use in the data processing produces more precise and realistic results. The measurement of the wall parameters is challenge in a… (More)