Mile Stojčev

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The electronics industry has entered the era of multi-million-gate chips, and thereXs no turning back. This technology promises new levels of integration on a single chip, called the System-on-a-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a single chip, may number well into the high tens within the(More)
In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this(More)
Performance and fault tolerance, FT, are two dominant issues during development of complex real-time embedded systems, RT_ES. FT is generally accomplished by using redundancy in hardware, software, time, or combination thereof. Triple modular redundancy, TMR, is one of the most popular FT hardware scheme which uses spatial redundancy. In this paper a design(More)
In this article we describe one suitable approach that enables the designer to insert a boundary-scan and built-in-self-test concepts, as typical design-for-testability techniques in system-on-chip and multichip module embedded system design, for fault-effects detection. For transient error detection implementation of parity error detection into a 36-bit(More)
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