Milad Hashemi

Learn More
Several researchers have recognized in recent years that today's workloads require a micro architecture that can handle single-threaded code at high performance, and multi-threaded code at high throughput, while consuming no more energy than is necessary. This paper proposes Morph Core, a unique approach to satisfying these competing requirements, by(More)
On-chip contention increases memory access latency for multicore processors. We identify that this additional latency has a substantial efect on performance for an important class of latency-critical memory operations: those that result in a cache miss and are dependent on data from a prior cache miss. We observe that the number of instructions between the(More)
Runahead execution pre-executes the application’s own code to generate new cachemisses. This pre-execution results in prefetch requests that are overwhelmingly accurate (95% in a realistic system con guration for the memory intensive SPEC CPU2006 benchmarks), much more so than a global history bu er (GHB) or stream prefetcher (by 13%/19%). However, we also(More)
The performance of user-facing applications is critical to client platforms. Many of these applications are event-driven and exhibit “bursty” behavior: the application is generally idle but generates bursts of activity in response to human interaction. We study one example of a bursty application, web-browsers, and produce two important(More)
Processor cores are seeing an increase in effective cache miss latency as the number of cores in a multi-core chip increases, and on-chip contention correspondingly increases. This paper identifies an important subset of latency-critical cache misses: those that will result in a cache miss but are dependent on a prior cache miss. We propose accelerating the(More)
  • 1