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Several researchers have recognized in recent years that today's workloads require a micro architecture that can handle single-threaded code at high performance, and multi-threaded code at high throughput, while consuming no more energy than is necessary. This paper proposes Morph Core, a unique approach to satisfying these competing requirements, by(More)
On-chip contention increases memory access latency for multi-core processors. We identify that this additional latency has a substantial eeect on performance for an important class of latency-critical memory operations: those that result in a cache miss and are dependent on data from a prior cache miss. We observe that the number of instructions between the(More)
—The performance of user-facing applications is critical to client platforms. Many of these applications are event-driven and exhibit " bursty " behavior: the application is generally idle but generates bursts of activity in response to human interaction. We study one example of a bursty application, web-browsers, and produce two important insights: (1)(More)
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