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Dictionary code compression is a technique which has been studied as a method to reduce the energy consumed in the instruction fetch path of processors. Instructions or instruction sequences in the code are replaced with short code words. These code words are later used to index a dictionary which contains the original uncompressed instruction or an entire(More)
The design time of System-on-a-Chip (SoC) is today rapidly increasing due to high complexity and lack of efficient tools for development and verification. This article describes the design and implementation of a Multiproces-sor SoC (MSoC) conducted by three master students. We propose a generic platform generator as a way to reduce time-to-market and(More)
Computer system performance is highly dependent on high access rate and low miss rate in the instruction cache, which also have implications on energy consumed by fetching instructions. Simulation experiments on a small scalar processor typical for embedded systems show that up to 20% of the overall processor energy is consumed in the instruction fetch path(More)
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions. We present a new view of dictionary code compression for moderately high-performance processors for embedded applications. Previous work with dictionary code compression has(More)
This paper presents an extension to an existing instruction set architecture, which gains considerable reduction in power consumption. The reduction in power consumption is achieved through coding of the most commonly executed instructions in a short format done by the compiler based on a profile of previous executions. This leads to fewer accesses to the(More)
We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small(More)
This thesis presents implementation of an extension to an existing instruction set architecture, which gains considerable reduction in power consumption. The reduction in power consumption is achieved through coding of the most frequently executed instructions in a short format done by the compiler based on a profile of previous executions. This leads to(More)
Dictionary code compression has been proposed to reduce the energy consumed in the instruction fetch path of processors or to reduce program footprint in memory. With this technique, instructions, or instruction sequences, are in the binary code replaced with short code words that in run-time are replaced with the original instructions using the dictionary(More)
This document is the result of a Master Thesis in Computer Engineering, describing the analysis, specification and implementation of the first prototype of Socrates, a configurable, scalable and predictable platform for System-on-chip Multiprocessor system for real-time applications. The design time of System-on-a-Chip (SoC) is today rapidly increasing due(More)
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