Mihalis Psarakis

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The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies(More)
A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor(More)
EVER-INCREASING MARKET DEMANDS for higher computational performance at lower cost and power consumption continually drive processor vendors to develop new microprocessor generations. Every new generation incorporates technology innovations from different research domains, such as microelectronics, digital-circuit design, and computer architecture. All these(More)
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost(More)
Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by(More)
Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model. In this paper we introduce a method to calculate the CFM testability of a cell-based(More)
The extensive use of Systems-on-ProgrammableChips (SoPCs) in many application domains emphasizes the importance of analysing the vulnerability of the designs to singleevent upsets (SEUs) and proposing efficient low-cost mitigation approaches. Most SEU mitigation approaches proposed so far in the literature for SoPCs are based on the use of popular hardware(More)