Learn More
This paper proposes an efficient HDL library of processing units for generic and DVB-S2 LDPC decoders following a modular and automatic design approach. General purpose, low complexity and high throughput bit node and check node functional models are developed. Both full serial and parallel architecture versions are considered. Also, a dedicated functional(More)
— State-of-the-art decoders for DVB-S2 low-density parity-check (LDPC) codes explore semi-parallel architectures based on the periodicity 360 M = factor of the special type of LDPC-IRA codes adopted. This paper addresses the generalization of a well known hardware M-kernel parallel structure and proposes an efficient partitioning by any factor of M, without(More)
  • 1