Michele G. Vieira

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A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by(More)
In this paper, we propose a new approach for using Built-in Current Sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition,(More)
The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track.This work presents an accurate and computer efficient analytical model for the evaluation of(More)
An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level(More)
Radiation effects, like Single Event Transients (SET), are increasingly affecting integrated circuits as device dimensions are scaling down. With decreasing dimensions and supply voltages, the charge used to store information decreases, turning the circuits more sensitive to the transient currents generated by energetic particle hits. This is particularly(More)
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