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Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure only a maximum of 10<sup>7</sup> - 10<sup>8</sup> writes, making a PCM based system have a lifetime of only a few years under ideal conditions. Furthermore, we show that(More)
Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X,(More)
Phase Change Memory (PCM) is emerging as a promising technology to build large-scale main memory systems in a cost-effective manner. A characteristic of PCM is that it has write latency much higher than read latency. A higher write latency can typically be tolerated using buffers. However, once a write request is scheduled for service to a bank, it can(More)
Phase Change Memory (PCM) is emerging as a scalable and power efficient technology to architect future main memory systems. The scalability of PCM is enhanced by the property that PCM devices can store multiple bits per cell. While such Multi-Level Cell (MLC) devices can offer high density, this benefit comes at the expense of increased read latency, which(More)
—In this paper, we investigate the ultimate performance limits, in terms of achievable information rate (IR), of communication systems impaired by impulse noise. We compare single carrier (SC) and multi-carrier (MC) transmission systems employing quadrature amplitude modulation (QAM) formats. More precisely, we consider SC schemes with coded modulations and(More)
We study memories capable of storing multiple bits per memory cell, with the property that certain state transitions &#x201C;wear&#x201D; the cell. We introduce a model that is relevant for Phase Change Memory, a promising emerging nonvolatile memory technology that exhibits limitations in the number of particular write actions that one may apply to a cell(More)
—The block erase requirement in NAND Flash devices leads to the need for garbage collection. Garbage collection results in write amplification, that is, to an increase in the number of physical page programming operations. Write amplification adversely impacts the limited lifetime of a NAND Flash device, and can add significant system overhead unless a(More)
—In this paper, we consider serially concatenated schemes with outer novel and efficient low-density parity-check (LDPC) codes and inner modulations effective against channel impairments. With a pragmatic approach, we show how to design LDPC codes tailored for simple and robust modulation formats, such as differentially encoded (DE) modulations. The LDPC(More)
In this paper, we consider multiple access schemes with correlated sources, where a priori information, in terms of source correlation, is available at the access point (AP). In particular, we assume that each source uses a proper low-density parity-check (LDPC) code to transmit, through an additive white Gaussian noise (AWGN) channel, its information(More)
—A fundamental constraint in the use of newer NAND Flash devices in the enterprise space is the low cycling endurance of such devices. As an example, the latest 2-bit MLC devices have a cycling endurance ranging from 3K to 10K program/erase cycles. Upcoming higher-density devices are expected to have even lower endurance. In this paper we propose a coding(More)