Michele Fabiano

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—Testing NAND flash memories is a very complex issue due to the rapid scaling down of the technology and the related floating gate reliability issues: as a consequence a complete and technology independent test is needed. Several faults and disturbances were identified both for NOR and NAND flash memories: however they has never been considered together as(More)
In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization(More)
obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Abstract – Designing a mass-memory device (i.e., a(More)
—Tackling the design of a mission-critical system is a rather complex task: different and quite often contrasting dimensions need to be explored and the related trade-offs need to be evaluated. Designing a mass-memory device is one of the typical issues of mission-critical applications: the whole system is expected to accomplish a high level of(More)
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