Michele Cassiano

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This paper presents a design methodology suitable for the cost-effective and real-time implementation of non-linear image processing algorithms. Starting from high-level functional descriptions the proposed optimization flow simplifies the designer's duty to achieve a low complexity and low power realization in CMOS technology (FPGA and/or ASIC) with low(More)
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like filters. Starting from high level descriptions, first algorithmic optimization is accomplished. Then a processor architecture and an instruction set are customized with special(More)
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