Michal Varchola

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We demonstrate a new high-entropy digital element suitable for True Random Number Generators (TRNGs) embedded in Field Programmable Gate Arrays (FPGAs). The original idea behind this principle lies in the randomness extraction on oscillatory trajectory when a bistable circuit is resolving a metastable event. Although such phenomenon is well known in the(More)
In this paper we present compact FPGA-based architectures for standardized elliptic curve cryptography over prime fields. Our approach differs from the many previous works due to the following design principles: First, we minimized storage by efficiently using block memories instead of registers, and second, we focused on elliptic curves based on(More)
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is built on three main blocks embedded soft-core with industry standard ARM7 architecture, internal Flash and static RAM memory blocks and custom True Random Number Generator (TRNG)(More)
The paper presents a novel hardware block that can be used for simultaneous generation of random bits and PUF responses. The new element called Universal Transition Effect Ring Oscillator (UTERO) is based on the TERO loop presented at CHES 2010. The PUF response bit corresponds to the output value of the TERO loop that converges to a state determined by the(More)
Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in field programmable gate arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. The paper analyses the jitter generated in ring oscillators and it uses a simple physical model of(More)
This paper deals with an evaluation platform for cryptographic True Random Number Generators (TRNGs) based on the hardware implementation of statistical tests for FPGAs. It was developed in order to provide an automatic tool that helps to speed up the TRNG design process and can provide new insights on the TRNG behavior as it will be shown on a particular(More)
The paper presents hardware SoPC platform for testing performance of various TRNGs embedded in Actel FPGAs. The SoPC was implemented in the recent Actel Fusion ARM enabled FPGA device. It consists of four main blocks CoreMP7 (Actel’s soft-core industry standard ARM7 processor) for managing the SoPC, SRAM and Flash memories embedded inside the FPGA for(More)
We present and analyze a new method of randomness extraction using logic gates only for FPGAs. Random behavior was observed in a ransition Effect Ring Oscillator. This oscillator consists of even number of inverting elements and even number of XOR gates. The first input of XOR is employed in Ring Oscillator chain and the second (control input) is used for(More)
We present the FPGA-optimized implementation of the statistical tests for evaluating sufficient quality of the embedded True Random Number Generator output. Tests are fully compatible the FIPS 140 standard and are implemented in the Actel Fusion FPGA. Hardware can run up to 109 MHz clock frequency and can process one random bit per one clock period. Whole(More)