Michael Yoeli

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Making formal verification a practicality in industrial environments is still difficult. The capacity of most verification tools is too small, their integration in a design process is difficult and the methodology that should guide their usage is unclear. This paper describes a step-by-step methodology which was developed for the practical application of(More)
Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, and unde f ined states;(More)
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various levels by a CSP-like language. The architectural features include decoupled data and branch processors, delayed branches with variable delay, unified data path and control,(More)