Michael Pabst

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This paper presents RESIST, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches , it ezploits the fact that many paths in a circuit have common subpaths. RESIST sensitizes those subpaths only once, TedUCing the number of value assignments dun'ng path sensitization(More)
Synthesis of testable sequential circuits has been proposed recently as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies {CRS) and sequential redundancies (SRS). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault(More)
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