Michael Ogbonna Esonu

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A systematic approach of designing fault-tolerant systolic architectures is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of the three versions of the algorithm.(More)
The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation(More)
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