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This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adders and multipliers are suggested and new converters for the residue signed-digit number system are described for the moduli . By extending an existing efficient signed-digit adder… (More)
This report presents a design space mapping of common arithmetic units with a 0.13 μm CMOS process technology. A behavioural vs. structural (gate-level logic) code comparison is made on key arithmetic functions, binary modulo arithmetic is studied and a brief complexity evaluation is made.
The purpose of this master's thesis was to explore the circuit design space (speed, area, power) of conventional binary arithmetic and to suggest improvements or alternatives to this arithmetic. The alternatives to the binary arithmetic focused on was the Signed-Digit (SD) number system, the Residue Number System (RNS) and the combination of these two… (More)