Learn More
In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes of current pulses generated due to particle strike. The(More)
In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients (SET)(More)
The author presents efficient self-checking implementations for adders and ALUs (ripple carry, carry lookahead, carry skip schemes). Among all the known self-checking adders and ALUs the parity prediction scheme has the advantage to require the minimum overhead for the adder/ALU and the minimum overhead for the other data path blocks. It has also the(More)
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result on unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting on increasing number of timing(More)