Michael M. Oshima

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—We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransport™ (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We(More)
A low-jitter charge-pump PLL is built in 90-nm CMOS for 1–10 Gb/s SerDes transmitter clocking. The PLL employs a programma-ble dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized(More)
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