Michael M. Oshima

  • Citations Per Year
Learn More
We present an 8.0-Gb/s HyperTransportTM technology I/O built in a 32-nm SOI-CMOS processor for highperformance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate highfrequency jitter in the received(More)
We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransport<sup>TM</sup> (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin(More)
As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be(More)
We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransportTM (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We(More)
A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized(More)
  • 1