Michael L. Bushnell

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In this paper, we study delay fault modeta and the corresponding test generation methodology for general sequential circuits. Our test generation method Is based on transzlion and hazard states of signals and is applicable to any sequential circuit irrespective of its structure, including the circuits where the flipflops can form a scan register. No hold(More)
Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the <i>dynamic power cutoff technique</i> (DPCT). First, the switching window for each gate, during which a(More)
W e present new extensions t o the EST' algoritlm, which accelerates combinational circuit Redundancy Identification and Automatic Test Pattern Generation ( A T P G ) algorithms, in particular SOCRATES. E S T detects equivalent search states, which are saved. for all faults during A T P G . The search space is reduced by using learned Search State(More)
We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified into three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modifying or(More)
An efficient <italic>Module Area Estimator</italic> for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for Standard-Cell and Full-Custom layout methodologies. We discuss the structure of the estimator and its algorithms. The layout area estimates are very close to(More)