Michael A. Lai

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The Asynchronous Array of Simple Processors (AsAP) uses processor cores with small instruction and data memories to dramatically reduce area and power while increasing performance. Fig. 23.6.1 shows the architecture of an individual AsAP processor and the 6×6 array contained on the chip. Data enters the array through the upper left processor and exits from(More)
An array of simple programmable processors is implemented in 0.18 m CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 mm and is fully functional at a clock rate of 520–540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW(More)
This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energyefficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication(More)
This dissertation investigates the architecture design, physical implementation, result evaluation, and feature analysis of a multi-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with(More)
Two methods for partial vectorization are implemented in the state-of-the-art optimizing open-source Open64 compiler. The first method vectorizes isomorphic expression trees in a basic block using tree matching. Given that finding isomorphic trees in a basic block is fast, the compile time overhead for this approach is negligible. The second method computes(More)
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