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As microprocessors begin to leverage multi-core functionality, the power consumption incurred from tag comparison in cache hierarchy of Chip Multi-Processors (CMPs) becomes more prevalent. In this paper, a novel two-level cache architecture is explored to reduce the tag comparisons for mitigating power overhead. For one thing, a way-tagged L1 cache is(More)
A SDRAM like conventional memories can be affected by the occurrence of single event upsets (SEUs) which can lead to serious faults such as single-bit error. In order to cope with this effect of SEUs, a fault-tolerant SDRAM controller is proposed instead of previous approaches that required modifications to the internal structure of the SDRAM itself. For(More)
The complexity of explicit parallel programming greatly limits programmers to achieve further performance gain in chip-multiprocessors (CMPs). To simplify software programming for large scale CMPs, we present a task-level superscalar microarchitecture which acts as the Control Processor (CP) of the Multi-Level Computing Architecture (MLCA), a novel(More)
Register renaming is an indispensable technique to cope with false data dependencies in out-of-order processors. The critical component for performing register renaming is a register alias table (RAT), which maintains the mappings between architecture and physical registers. Unfortunately, a potential misprediction may seriously slower the processor(More)
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