Meryem Marzouki

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This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture , which is dynamically reconfigurable, scalable and flexible , is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified(More)
The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its flexibility, scalability and reconfigurability. It also allows trade-off to optimize test time and area overhead.(More)
This paper describes CAS-BUS, a P1500 compatible Test Access Mechanism for Systems on a Chip. The TAM architecture is made up of a Core Access Switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE(More)
Diagnosing analog circuits with their numerous known difficulties is a very hard problem. Digital approaches have proven to be inappropriate, and AI-based ones suffer from many problems. In this paper we present a new system, FLAMES, which uses fuzzy logic, model-based reasoning, ATMS extension, and the human expertise in an appropriate combination to go(More)
This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testabil-ity, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be proposed(More)
This paper details our allocation for Built-in Self Test (BIST) technique used in the Interactive Design for Test reuse in Allocation for Testability (IDAT) tool. IDAT tool objective is to fullll the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a(More)