Meng-Lieh Sheu

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SEQUENTIAL TEST generation poses a difficult problem for circuits implemented from finite-state machines. The flip-flops in sequential circuitssynthesized from FSMs generally have intricate cyclic structures that complicate sequential test generation. We have developed a parity checker design-fortestability scheme that significantly enhances circuit(More)
In this paper, a low parasitic capacitance and low-power CMOS capacitive fingerprint sensor readout circuit is presented. The side effect of parasitic capacitance has been under control with novel layout structure in sensor cell, and minimal size switch is used to reduce non-ideal effects of MOS switch and achieve good linearity. Power dissipation is also(More)
A new multiple-sequence generator scheme to generate a set of deterministic ordered sequence of patterns followed by random patterns is presented in this paper. This scheme is based on an inverted nonlinear autonomous machine which utilizes a twodimension-like LFSR with nonlinear inverters. A systematic procedure is also presented to obtain the autonomous(More)