Meng-Lieh Sheu

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SEQUENTIAL TEST generation poses a difficult problem for circuits implemented from finite-state machines. The flip-flops in sequential circuitssynthesized from FSMs generally have intricate cyclic structures that complicate sequential test generation. We have developed a parity checker design-for-testability scheme that significantly enhances circuit(More)
In this paper, an integrated passive device (IPD) inductor modeling is demonstrated. The IPD technology is a system in package (SiP) solution where passive devices with high quality can be fabricated on a chip and then connect with another circuit chip by using flip-chip micro-bump bonding. For an RF circuit simulation, the IPD inductor model is built and(More)
Space-time block codes are considered as one of the prominent technologies for spatial diversity which is widely used to improve wireless system performance. However, an OFDM system with space-time block codes needs multiple fast Fourier transforms (FFT) posing an adverse effect on system computational load as the number of antennas and sub-carriers grows.(More)
A 10-bit successive approximation ADC for low voltage and low power applications is proposed in this paper. The chip operating voltage is 0.7 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayered sandwich capacitor array is used in the digital to analog converter employed in the ADC to reduce the overall capacitance value and(More)