Meng-Chen Wu

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To facilitate sequential data transfer (e.g., bus or pipeline signals) and reduce bounded net delay (as well as total wirelength), it is desired to align circuit blocks one by one and constrain the blocks within a certain bounding box. In this paper, we handle the placement with alignment and performance (delay) constraints using the B*-tree representation.(More)
— Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize(More)
Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize(More)
A 60-year-old man with a history of atrial fibrillation had an acute onset of ballistic movements of the left limbs with sensory extinction (video on the Neurology® Web site at www.neurology.org). The patient was treated with risperidone and anticoagulant; symptoms subsided 3 days later. Brain MRI showed acute infarction of the right posterior parietal lobe(More)
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