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An ILP formulation for application mapping onto Network-on-Chips
Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically sinceExpand
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Application mapping algorithms for mesh-based network-on-chip architectures
Due to shrinking technology sizes, more and more processing elements and memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus orExpand
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Genetic algorithm based NoC design with voltage/frequency islands
Due to increasing complexity of the embedded applications, designing a Network-on-Chip (NoC) architecture under energy, cost, and performance constraints has become challenging issue. Especially,Expand
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