Melchiorre Bruccoleri

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A new approach to analog VLSI implementations of algorithms for visual cortical processing is presented. Speciically, we introduce a massively parallel architecture , organized as a planar resistive network with voltage controlled current generators locally connected to model interaction schemata responsible of speciic sensitivities in cortical neurons. We(More)
FIR filters are attractive to enhance the equalization performances of high speed wireline receivers, providing high flexibility to match the channel frequency response and compatibility with simple adaptation techniques. This paper presents a 25-Gb/s 4-tap FIR equalizer in 28-nm LP CMOS. To keep high SNR and not compromise equalization performances, a new(More)
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