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Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard(More)
This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and(More)
This paper focuses on prototyping pausible and gated In this paper, after presenting an overview on the pausible clock based GALS systems on commercial FPGAs. Pausible clock clock based and gated clock based GALS systems in sections II based GLAS systems use an on-chip clock generator to generate and III, the implementation of GALS on commercial FPGA(More)
Keywords: Cryptography Side channel attack Asynchronous design Low power QDI a b s t r a c t Regarding the significant mathematical immunity of recent cryptographic algorithms, attacks considering the physical aspects of these algorithms, known as side channel attacks, have received much of interest. Today, it is quite clear that asynchronous circuits(More)
An efficient adaptive method to perform dynamic voltage and frequency management (DVFM) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFM system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to(More)
In this paper we propose an asynchronous wrapper with new asynchronous communication port controllers and reliable clock generation scheme for locally synchronous modules. This is achieved by utilizing clock gating idea within GALS wrappers which makes the use of reliable and robust off-chip clock generator possible for locally synchronous modules. In(More)
In this paper, we present a new efficient methodology for power estimation of the well known family of asynchronous circuits, QDI circuits, at pre-synthesized level. Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concurrent processes represented with CSP-Verilog. The number of Reads(More)
This paper focuses on a clock generation scheme for implementation of GALS circuits on commercial FPGAs which are mostly synchronous. Previously overlooked timing problems of existing pausible clock generators are explored and a novel clock generator is introduced. To validate the proposed solution we implemented the clock generator and a simple port(More)