This paper presents an in-depth study of a 45-nm CMOS silicon-on-insulator (SOI) technology. Several transistor test cells are characterized and the effect of finger width, gate contact, and gate poly pitch on transistor performance is analyzed. The measured peak ft is 264 GHz for a 30 × 1007 nm single-gate contact relaxed-pitch transistor and the… (More)
This paper presents low-noise amplifiers (LNA) at 45¿C95 GHz, a frequency doubler at 180 GHz, active and passive mixers at 130¿C180 GHz fabricated in 45-nm Semiconductor-On-Insulator (SOI) CMOS process for digital and mixed-signal applications. The measured ft and fmax of a 30¡A1-¿Im transistor are 200 GHz at 0.3 mA/¿Im current density, referenced to the… (More)
The chip was tested up to 105°C and maintained > 3 Gbps with a BER < 10-12 over the entire temperature range.
This paper presents an in-depth analysis of an SiGe BiCMOS on-off keying (OOK) receiver composed of a low-noise SiGe amplifier and an OOK detector. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. The LO leakage from the transmitter can also have a… (More)
measured P 1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than-8 dB at 50-70 GHz. The active chip area is 0.5x0.55 mm 2 and can be reduced in future designs by folding the on λ/4 transmission lines. To our knowledge, this paper presents the lowest insertion loss 60 GHz SPDT in any CMOS technology to-date.