In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are… (More)
In this paper, we propose a two-tier method for extracting fetal ECG from a single lead abdominal ECG signal. The proposed method is based on a combination of singular value decomposition (SVD) and polynomial classifiers. As a first tier, SVD is used to extract an estimate of the maternal component from the composite abdominal signal by exploiting its… (More)
In this paper we propose a new architecture Physical Random Functions (or Physical Unclonable Functions, PUFs) to create a candidate hardware random number generator. So far several random number generators based on ring oscillators were introduced but all of them have either security or stability problems. This paper presents a novel architecture which has… (More)
A fully integrated charge-pump phase-locked loop (PLL) is described. The PLL is designed and simulated in a 0.13 CMOS technology. The PLL lock range is from 100MHz to 1.66GHz.
In this paper, a blind video watermarking algorithm based on 3D wavelet transform and Human Visual System (HVS) model is proposed. The proposed method is based on extracting temporal characteristics of video signal and using it to adjust spatial features of each frame. These frames are designed based on HVS model embed the message. Then the message will be… (More)
Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency… (More)