Mayurika Chatterjee

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
A new approach to designing random pattern testable logic circuits is introduced. The synthesis methodology proposed here begins with a multi-level circuit and synthesizes the circuit, optimizing its area and enhancing its random pattern testability. The method is based on ATPG-based transformations. A scheme is presented to guide the synthesis process and(More)
  • 1