Mayumi Nakasato

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We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the(More)
We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the(More)
We have developed a multilayer substrate that is formed from a high thermal conductive resin including ceramic fillers at high density in order to realize a module that is more miniaturized and has lower thermal resistance. First, we realized a resin with a very high filler filling rate of 75% by mixing two kinds of spherical fillers different in particle(More)
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