Mayukh Bhattacharya

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Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device(More)
This paper describes the incorporation of an accurate physics-based model of the resonant tunneling diode (RTD) into Berkeley SPICE version 3F5 and addresses the related direct current (dc) and transient convergence problems caused by the negative differential resistance (NDR) and the exponential nature of the device characteristics. To circumvent the dc(More)
This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differential-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR(More)
In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool, first proposed in [3], designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in(More)
Threshold gates consisting of resonant tunneling diodes (RTDs) in conjunction with HBTs or CHFETs or MOSFETs can form extremely compact, ultrafast, digital logic alternatives, and may be used for digital signal processing applications in the near future. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching(More)
A novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented.