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A design step transforms a specification into an implementation and may take place on several levels of abstraction. If we want to formally capture the design step in order to reason about its correctness we need on the one hand formal VHDL semantics capturing the static and dynamic aspects of the VHDL simulation model. On the other hand, we need special(More)
Several hardware compilers on the market convert from so-called RT level VHDL subsets to logic level descriptions. Such models still need clock signals and the notion of physical time in order to be executable. In a stage of a top-down design starting from the algorithmic level, register transfers are considered, where the timing is not controlled by clock(More)