Matthias Kühnle

Learn More
The efflux pumps ABCB1 (p-gp, MDR1) and ABCG2 (BCRP) are expressed to a high extent by endothelial cells at the blood-brain barrier (BBB) and other barrier tissues and are involved in drug resistance of tumor (stem) cells. Whereas numerous ABCB1 inhibitors are known, only a few ABCG2 modulators with submicromolar activity have been published. Starting from(More)
Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of(More)
Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that(More)
Reconfigurable architectures and NoC (network-on-chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adap-tivity through run-time reconfiguration, opens a new area of(More)
An innovative technique to model and simulate partial and dynamic reconfiguration is presented in this paper Developed from modifications of the SystemC kernel, this technique can either be used at transaction level (TLM) or at register transfer level (RTL). At TLM it allows the modeling and simulation of higher-level hardware and embedded software, while(More)
The presented paper describes an approach of dynamic positioning of functional building blocks on Virtex (Xilinx) FPGAs. The modules can be of a variable rectangular shape. Further, the on-chip location of the area to be reconfigured can be freely chosen, so that any module can be placed anywhere within the defined dynamic region of the FPGA. Thus the(More)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for dynamic reconfiguration. The presented approach can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or(More)
A good harware design requires both competent theoretical as well as practical knowledge in the areas of architecture specification and design. While the theoretical background is given in several lectures gaining practical knowledge is somewhat more difficult. To face this problem a laboratory has been established. Analog as well as digital hardware(More)
The exponential increase of CMOS circuit complexity along the last decades has lead to two growing problems. The increasing Non-recurring Engineering (NRE) costs of ASICs or System-on-Chips are becoming only affordable to the highest volume applications. Additionally the design methodologies have not kept pace with the rising complexity leading to a rising(More)