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This paper reports a 45nm spin-transfer-torque (STT) MRAM embedded into a standard CMOS logic platform that employs low-power (LP) transistors and Cu/low-k BEOL. We believe that this is the first-ever demonstration of embedded STT MRAM that is fully compatible with the 45nm logic technology. To ensure the switching margin, a novel “reverseconnection” 1T/1MT(More)
Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge(More)
Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1<i>ns</i> to 100<i>ns</i> have been reported for STT-RAM. The switching current of magnetic tunnel junction (MTJ) (which is the storage element of STT-RAM) is inversely(More)
Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process(More)
As CMOS technology is scaled beyond 45nm, SOC/SiP design for wireless chips is increasingly constrained by fundamental technology limits, resulting in challenges including parametric variability, leakage, active power, signal integrity, and diminished performance improvement. New materials and innovative device structures are needed to extend CMOS scaling(More)
A comparison of two separation columns for high-capacity anion chromatography is presented. The distinctive feature of both packing materials is the structure of the alkyl-chain (spacer-group) between the polymer-backbone and the functional group. All other parameters, e.g. exchange capacity, functionality and length of the spacer-arm, are identical. The(More)
Power/signal delivering network for 2D systems comprising a package and an Integrated Circuit (IC) are design tasks that can be concurrently handled today. Design iterations can be locally carried out in each subsystem part without the need to modify the other one's decisions. This is unfortunately not the case in 2.5D/3D stacked systems. Finer system(More)
A novel elution system for the application of high-capacity anion exchangers with suppressed conductivity detection in ion chromatography is presented. The ternary elution system is based on perchloric acid, sodium hydroxide and sodium carbonate. The novel elution system was applied to a self-made high-capacity anion-exchange column (Q = 453 mu equiv. Cl-).(More)