Matías J. Garrido

Learn More
In this paper the implementation of an H.263 base-line video coder on an FPGA-based platform is explained. The coder consists of a set of specialised processors for the main tasks (DCT, quantizations, motion estimation) and a RISC for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware-software(More)
In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multi-format set-top box is described. Baseline and main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance with(More)
In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture consists of 256 processor elements, deals with a search area of -8/+7 pels and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is(More)
Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed.(More)
High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H.264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of(More)
Currently, the usefulness of many mobile systems is largely limited by the battery lifetime. In this paper, energy-based fair queuing (EFQ) is proposed as a pivotal instrument to maximize the user experience in this type of system. Energy-based fair queuing is a novel class of energy-aware scheduling algorithms that support proportional energy use,(More)
In this paper, the implementation of a Main Profile H.264 decoder based on a DM642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm(More)
In this paper, the implementation of a digital signal processor (DSP) based Internet protocol set-top box for home entertainment networks is described. The main functional blocks are the MPEG-2 transport stream demultiplexer, the audio and video decoders and the audio and video display management modules (with on-screen display capabilities). All blocks(More)
In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over digital audio broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a personal computer via an USB port. We have implemented the system on an FPGA(More)
During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new(More)