Massimiliano Chiodo

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Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating Finite State Machines provide a convenient intermediate format for embedded system co-synthesis, between high-level speciication languages and software or hardware implementations. We propose a software generation methodology(More)
Hardware/software co-simulation is generally performed withseparate simulation models.This makes trade-off evaluationdifficult, because the models must be re-compiled wheneversome architectural choice is changed.We propose a techniqueto simulate hardware and software that is almost cycle-accurate,and uses the same model for both types of components.Only the(More)
| Current design methodologies for embedded systems often force the designer to evaluate early in the design process architectural choices that will heavily impact the cost and performance of the nal product. Examples of these choices are hardwareesoftware partitioning, choice of the micro-controller, and choice of a run-time scheduling method. This paper(More)
We describe a method for reducing the complexity of CTL model checking on a system of interacting finite state machines. The method consists essentially of reducing each component machine with respect to the property we want to verify, and then verifying the property on the composition of the reduced components. The procedure is fully automatic and produces(More)
Embedded systems are typically implemented as a set of communicating components some of which are implemented in hardware and some of which are implemented in software. Usually many software components share a processor. A real-time operating system (RTOS) is used to enable sharing and provide a communication mechanism between components. Commercial RTOSs(More)
We propose a software synthesis procedure for reactive real-time embedded systems. In our approach, control parts of the system are represented in a decomposed form enabling more complex control structures to be represented. We propose a synthesis procedure for this representation that incrementally aggregates elements of the representation while keeping(More)