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Journals and Conferences
A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25m CMOS technology and occupies a total silicon area of 23 mm. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall… (More)
A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure, and 112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.
A tunable high-Q RF filter suitable for wireless transmitters has been implemented in standard CMOS technology. Two stagger-tuned Q-enhanced resonators form a filter that can be tuned across frequency and bandwidth. A 5.145-GHz filter with 200-MHz bandwidth and 0.8-dB of ripple is demonstrated in an 802.11a sliding-IF transmitter. The transmitter provides… (More)
This paper presents the design of a dual-band, tri-mode wireless LAN chipset for IEEE 802.11a/b/g. The chipset, designed in 0.25/spl mu/m standard CMOS, features a 5GHz RF transceiver, a 2.4GHz RF transceiver, and a baseband processor with media access controller. The overall design achieves a measured sensitivity of at least -70dBm at 54Mbps and -92dBm at… (More)
The paper presents the challenges involved in the design of integrated IEEE 802.11 wireless LAN transceivers with focus on radio architecture and circuit implementation. In particular, examples of critical blocks in the receiver and transmitter are discussed.
Enabling Gb/s throughputs in wireless LAN systems require significant upgrades to the 802.11 standard. which in turn brings new challenges for the radio designers. This paper describes some of these challenges and potential solutions.