Masayuki Ikebe

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A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing(More)
We propose a new method of canceling the fixed-pattern noise of CMOS activepixel image sensors caused by the threshold mismatch of MOS FETs in pixel circuits. This method uses with non-destructive intermediate readout circuitry. Assuming a TSMC 0.25-μm mixed-signal process, we designed a CMOS image sensor in which the canceling circuit was implemented for(More)
We propose a O(1) algorithm for bilateral filter with low memory usage. Bilateral filter can be converted into weighted histogram operation. Applying line buffers of column histograms, we can reduce the number of calculation needed to construct recursive center-weighted local histogram. Also our method have advantage in terms of memory requirements. We used(More)
We will describe a cellular-automaton (CA) LSI that extracts quadrilateral objects, such as box areas filled with the same pixel values, from binary images. We propose an efficient CA algorithm, based on the reaction-diffusion chemical systems model. Each cell in the proposed CA is implemented by a digital circuit called an elemental processor. The CA LSI(More)
We propose a method for improving the accuracy of histogram-based image filtering. With this method, we define a histogram called intensity-stacked histogram. An image histogram generally consists of a frequency (number of pixels) for each bin. On the other hand, intensity-stacked histogram stores the sum of intensity values for each bin. The(More)
Silicon circuits that mimic the nervous systems of insects and other animals represent the future of neurocomputing. They can perform various neural functions because the microstructures of a nervous system are replicated on their silicon chips. Since recent functional models of spiking neural networks tend to use spiking neurons, neuromorphic engineers(More)
This paper presents a novel hardware-oriented stereo vision system based on 1-D cost aggregation. Many researchers have implemented hardware efficient stereo matching to realize real-time systems. However, such methods require a large amount of memory. We proposed a system that is based on a hardware-software hybrid architecture for memory reduction. It(More)
We discuss a cellular-automata (CA) LSI core that extracts early features of objects in images, such as sizes and skeletons. A CMOS-image sensor with a CA core enables high-speed image processing. We propose an efficient CA algorithm based on rotated template matching. Each cell circuit in the proposed CA is implemented by a digital circuit, and transistors(More)