Masatomo Kawano

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  • M. Kawano
  • 2007
A 3D packaging technology has been developed for high-density stacked DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The(More)
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