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This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed(More)
A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has(More)
As the variations of shrunk processes increasing at rapid rate, the performances of analog/mixed-signal chips remarkably fluctuate. It is necessary to take the yield as a design objective in design optimization. This paper presents a novel method to generate yield-embedded Pareto-front to simultaneously optimize both the yield and performances. Unlike the(More)
This paper presents a new method using multi-objective optimization algorithm to automatically find the <i>best solution</i> from a <i>topology library</i> of analog circuits. Firstly this method abstracts the Pareto-front of each topology in the library by SPICE simulation. Then, the Pareto-front of the <i>topology library</i> is abstracted from the(More)
A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator operates twice each cycle, during coarse and fine decision, for a conversion based on digitally controlled threshold levels. The threshold levels at these decisions are different, so these are adjusted(More)
This paper presents a new method using multi-objective optimization algorithm to automatically find the best solution from a topology library of analog circuits. Firstly this method abstracts the Pareto-front of each topology in the library by SPICE simulation. Then, the Pareto-front of the topology library is abstracted from the Pareto-fronts of topologies(More)
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